Using High-Level Synthesis to Implement the Matrix-Vector Multiplication on FPGA

Il lavoro è stato preparato da Paolo Palazzari e da Alessandro Marongiu e verrà presentato al prossimo ISC 2020, High Performance 2020 Digital dal 22-25 giugno 2020.

ISC2020_rev4

ISC2020_slides

Inoltre sono disponibili i proceedings di ISC 2020:
“All accepted ISC 2020 research papers are published in the Springer’s Lecture Notes in Computer Science (LNCS) series. LNCS 12151 is available at https://link.springer.com/book/10.1007/978-3-030-50743-5.
The download is for free from June 20 to July 20.”